1. Field of the Invention
This invention is related to the field of processors and, more particularly, to register window management in processors.
2. Description of the Related Art
Typically, processors implement pipelines to perform the instruction execution process. A pipeline comprises multiple pipeline stages, each of which is assigned one or more operations in support of the overall instruction execution. Different instructions may be in different pipeline stages concurrently, increasing performance by overlapping the execution of the instructions. In some processor designs, instructions of different types (e.g. integer, floating point, graphics, etc.) may have different numbers of pipeline stages. For example, integer pipelines often have fewer pipeline stages than floating point pipelines. The number of pipeline stages in a given pipeline is often referred to as the “depth” of the pipeline. While the pipelines may differ in numbers of stages, some stages may be shared between the pipelines. For example, pipeline stages that implement the fetch and decode of instructions (and sometimes the scheduling of instruction execution) may be shared between the pipelines in some cases.
Some instruction set architectures (ISAs) define the concept of register windows for the registers addressable by the instructions. Generally, the processor may implement a group of registers greater than the number of registers that are directly addressable using instruction encodings. A register window may be a subset of the implemented registers that are available for addressing by instructions at a given point in time. Registers in the currently-active register window (usually referred to as the “current register window” or simply the “current window”) are mapped to the register addresses that can be specified in the instructions. If the current register window is changed to another register window, the registers addressable by instructions are changed.
Register windows may be used to accelerate or simplify the processing of procedure calls and returns in some cases. Adjacent register windows may be defined to overlap in the implemented registers, such that some registers are included in both windows. The overlapping registers may be used to pass parameters between the calling procedure and the called procedure. When a procedure call is to be made, a save instruction may be executed that saves the register window of the calling procedure and provides a new, adjacent window for the called procedure. The called procedure may receive parameters in the overlapping registers. When a procedure return is to occur, a restore instruction may be executed to save the called procedure's register window and restore the calling procedure's register window. The overlapping registers may be used to return results of the called procedure.
For example, the SPARC® ISA defines a register window for 24 of the 32 addressable registers. The remaining registers are global registers which are not affected when the register window is changed. The save and restore instructions are defined to provide the user with the ability to change the current register window to an adjacent register window. Additionally, the save and restore instructions are defined to perform an add on source operands read from the “old” register window (prior to execution of the save/restore instruction) and to store the add result in the “new” register window (established via execution of the save/restore instruction).
The above definition of the save/restore instructions typically creates interlocks in the pipeline implemented by a processor to ensure that the sources are read from the old register window and the result of the add is written to the new register window. For example, if the changing from the old register window to the new register window requires more clock cycles than performing the add operation, then an interlock on the add operation is required to prevent writing the result until the new window is established. Interlocks often cause stalls in the pipeline, and may also be error-prone in implementation. Errors in implementing interlocks may result in erroneous operation of the processor, and may even result in livelock or deadlock.